The present disclosure relates to semiconductor devices and methods for fabricating the semiconductor devices, and more particularly to a semiconductor device obtained by performing burn-in, in a batch, on semiconductor integrated circuit devices on a semiconductor wafer, and a method for fabricating the semiconductor device.
A conventional semiconductor device is fabricated by electrically connecting a semiconductor integrated circuit device to leads of a lead frame with bonding wires and then encapsulating the semiconductor integrated circuit device and the leads of the lead frame with a resin or a ceramic material. Such a semiconductor device is mounted on a printed board, and is incorporated in electronic equipment.
The electronic equipment is required of having its cost reduced. Accordingly, cost reduction of the semiconductor device is also required. This requirement leads to a demand for supplying quality-guaranteed semiconductor devices at low cost.
To guarantee the quality of semiconductor devices, burn-in is generally employed. Preferred examples of burn-in include burn-in performed, in a batch, on a plurality of semiconductor integrated circuit devices on a semiconductor wafer (where such burn-in will be hereinafter also referred to as “wafer burn-in”). This burn-in can reduce the cost for burn-in, and also reduce the cost for apparatus for use in burn-in.
Such wafer burn-in is performed using a contactor with probe tips. Each of semiconductor integrated circuit devices formed on a semiconductor wafer is provided with testing electrode terminals, which are connected to the probe tips in the wafer burn-in.
In performing wafer burn-in, it is necessary to apply a power-supply voltage, a ground voltage, or a signal to the testing electrode terminals provided on each of the semiconductor integrated circuit devices. To individually apply a power-supply voltage, a ground voltage, or a signal to the testing electrode terminals provided in each of the semiconductor integrated circuit devices, a considerably large number of wires need to be drawn on contacts or the semiconductor wafer. For this reason, this technique is not practical. As another technique, it is proposed that a common power-supply voltage line, a common ground voltage line, or a common signal line (where these lines will be hereinafter collectively referred to as “common lines”) is provided on the contactor or the semiconductor wafer such that the common line is electrically connected to each of the testing electrodes. This technique can avoid the necessity of drawing a considerably large number of wires.
In such a case where the common line is provided on the contactor or the semiconductor wafer, however, a possible electrical short-circuit occurring in part of the semiconductor integrated circuit devices on the semiconductor wafer causes a short-circuit between the common power-supply voltage line and either the common ground voltage line or the common signal line through the short-circuited semiconductor integrated circuit device. To solve this problem, Japanese Patent Publication No. H07-169806 shows the following testing method. In this method, a test on electrical characteristics of each semiconductor integrated circuit device is performed prior to wafer burn-in. Then, an insulator resin is applied onto testing electrode terminals of a semiconductor integrated circuit device which has been determined to be defective in the test on electrical characteristics. Thereafter, wafer burn-in is performed.